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Job Description:

We are currently seeking an experienced ASIC Design Engineer with a strong focus on PCIe protocol, particularly in its physical layer. The ideal candidate will possess comprehensive system-level knowledge of PCIe, backed by hands-on experience in silicon bring-up and debugging involving the PCIe protocol. A robust background in ASIC design and proficiency in Verilog and SystemVerilog is required. The role demands a thorough understanding of Serializer/Deserializer (SerDes) technology and its application in high-speed data communication.

Job responsibilities include:

PCIe System Expertise:

• Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification.
• Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions.
• Deep understanding of PCIe retimer specification.
• Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues.

ASIC Design and Development:

• Design, implement, and verify ASIC components with a focus on PCIe physical layer requirements.
• Utilize Verilog and SystemVerilog for development, ensuring compliance with performance and design standards.

SerDes Technology:

• Extensive knowledge of SerDes technology, including understanding its operation, design challenges, and integration into high-speed communication interfaces.

Collaboration and Leadership:

• Work closely with cross-functional teams to drive the design process from concept to implementation.
• Provide guidance and expertise in PCIe-related discussions and decisions.

Quality Assurance and Validation:

• Ensure the highest quality of design through rigorous testing, validation, and adherence to industry standards.
• Document designs, analyses, and test results comprehensively.

Job Requirement:

• PhD plys 10+ years, or MSEE plus 13+ years, or BSEE plus 15+ years, equivalent experience in ASIC design and verification.
• Good Knowledge in languages relevant to the ASIC development process including Verilog, System Verilog, Unix/Perl Scripting or Python.
• Complete and full knowledge of PCIe protocol. Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification.
• Demonstrated experience in silicon bring-up and debug involving PCIe protocol.
• Design, implement, and verify ASIC components with a focus on PCIe physical layer requirements.
• Good knowledge of high speed digital circuit design.
• Good knowledge of RTL simulation and synthesis.
• Strong analytical and problem solving skills as well as hands-on lab debugging experiences
• In-depth knowledge for design for low power and design for test and design for manufacturing.
• Self-motivated, excellent communication skills and ability to excel in a team environment.
• Good organization skills, able to follow through & bring issue to closure
• Be able to work with teams at remote locations with different time zone. Detail-oriented with strong organizational and multitasking capabilities.
• Excellent problem-solving abilities and analytical mindset.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $147,000- $245,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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